1. Field
The present invention relates to a phase-locked loop circuit having a low-pass filter and a delay-locked loop circuit having a low-pass filter.
2. Description of Related Art
FIG. 16 is a block diagram showing an exemplary configuration of a phase-locked loop'circuit. The phase-locked loop (hereinafter, referred to as PLL) circuit has a phase comparator (PFD) 101, a charge pump 102, a low-pass filter (LPF) 103, a voltage-controlled oscillator (VCO) 104, and a frequency divider 105.
FIG. 17 is a circuit diagram showing an exemplary configuration of the voltage-controlled oscillator 104 in FIG. 16. The voltage-controlled oscillator 104 is, for example, a ring oscillator in which four VCO units 111 are ring-connected. Each VCO unit 111 has a variable resistor 1701, a differential amplifier 1702, and a current source 1703. The variable resistor 1701 is connected between a power supply voltage node and a power supply terminal of the differential amplifier 1702. The resistance value of the variable resistor 1701 changes according to a control voltage Vcntl.
FIG. 18 is a circuit diagram showing exemplary configurations of the low-pass filter 103 and the voltage-controlled oscillator 104 in FIG. 16. First, the configuration of the low-pass filter 103 will be described. The low-pass filter 103 is a passive low-pass filter having capacitors C1 and C2 and a resistor R1. A series-connected circuit including the capacitor C1 and the resistor R1 is connected between a power supply voltage node and a node of a control voltage Vcntl. The capacitor C2 is connected between a power supply voltage node and a node of the control voltage Vcntl.
FIG. 19 is a block diagram showing an exemplary configuration of a delay-locked loop circuit. The delay-locked loop (hereinafter, referred to as DLL) circuit has a phase comparator (PFD) 101, a charge pump 102, a low-pass filer (LPF) 103, and a voltage-controlled delay device (VCDL) 121.
FIG. 20 is a circuit diagram showing an exemplary configuration of the voltage-controlled delay device 121 in FIG. 19. The voltage-controlled delay device 121 is, for example, a delay line having four VCDL units 122. Each VCDL unit 122 has a variable resistor 2001, a differential amplifier 2002, and a current source 2003. The VCDL units 122 have the same configuration as the VCO units 111 in FIG. 17. Reference clock differential signals RCK1 and RCK2 are differential signals of a reference clock signal RCK in FIG. 19. Output clock differential signals TCK1 and TCK2 are differential signals of an output clock signal TCK in FIG. 19.
FIG. 21 is a circuit diagram showing exemplary configurations of the low-pass filter 103 and the voltage-controlled delay device 121 in FIG. 19. The low-pass filter 103 has the same configuration as the low-pass filter 103 in FIG. 18. The voltage-controlled delay device 121 has transistors M11 and M12 and four VCDL units 122. The transistors M11 and M12 have the same configuration as transistors M11 and M12 in FIG. 18. The VCDL unit 122 has the same configuration as a VCO unit 111 in FIG. 18. The four VCDL units 122 are connected in series as shown in FIG. 20.
In recent years, such a PLL circuit and a DLL circuit having high universality have been required. Hence, the voltage-controlled oscillator 104 oscillating over a broad band and the voltage-controlled delay device 121 requiring a wide-range delay have been developed.
As shown in FIGS. 17 and 18, the voltage-controlled oscillator 104 includes VCO units 111 in which a plurality of stages of CML ring elements are arranged and which apply positive feedback; and bias circuits M11 and M12 that supply a bias voltage to the ring elements. As shown in FIGS. 20 and 21, the voltage-controlled delay device 121 includes VCDL units 122 in which a plurality of stages of CR delay elements are arranged and which apply positive feedback; and bias circuits M11 and M12 that supply a bias voltage to the VCDL units 122. A control voltage Vcntl from the low-pass filter 103 is input to the bias circuits M11 and M12. The bias circuits M11 and M12 each output a bias voltage proportional to the control voltage Vcntl. The bias voltages control a tail current source transistor M27 and load transistors M22 and M23 of a CML. Though there is a scheme to control only load transistors or only a tail current source transistor, it is common practice to use a scheme to simultaneously control both, when a constant amplitude needs to be maintained regardless of the oscillation frequency. For the low-pass filter 103, in the case of charge pump PLL and DLL circuits, it is common practice for the low-pass filter 103 to include only passive elements. Depending on the application, the low-pass filter 103 may be an active filter.
However, in the case of the PLL circuit in FIGS. 17 and 18 and the DLL circuit in FIGS. 20 and 21, as a result of implementing a broad band or a wide-range delay, the PLL circuit and the DLL circuit have closed-loop function characteristics, such as those shown in FIG. 22.
FIG. 22 is a diagram showing closed-loop functions of the PLL circuit and the DLL circuit. A horizontal axis represents frequency and a vertical axis represents jitter gain. A function 2201 is a function with a lock frequency being 100 MHz. A function 2202 is a function with a lock frequency being 1 GHz. In the case of the PLL circuit, although the cutoff frequency is high at high frequencies, the cutoff frequency is low at low frequencies. A transition of the cutoff frequency indicated by an arrow 2203 affects jitter characteristics in FIG. 23.
FIG. 23 is a diagram showing jitter characteristics relative to frequency. For example, a PLL circuit that can lock in a range from 100 MHz to 1 GHz will be considered. The jitter characteristics as used herein indicate jitter that occurs due to device noise in the voltage-controlled oscillator 104. In a normal PLL circuit, the device noise in the voltage-controlled oscillator 104 is the main cause of jitter. In an ideal jitter characteristic 2301, the VCO gain is constant regardless of the frequency and thus jitter has a constant value. However, in an actual jitter characteristic 2302, the VCO gain decreases with low frequencies and thus jitter increases. The reason why such a problem occurs is that parameters called VCO gain and VCDL gain of the voltage-controlled oscillator 104 and the voltage-controlled delay device 121 fluctuate in the manner shown in FIGS. 24 and 25.
FIG. 24 is a diagram showing a control voltage Vcntl-oscillation frequency fosc characteristic 2400 of the voltage-controlled oscillator 104. The PLL circuit can lock in a frequency range TF in a tuning range RN. Vdd represents the power supply voltage and Vth represents the threshold voltage of transistors. When the control voltage Vcntl is V1, the oscillation frequency fosc is f1 and a VCO gain 2401 is represented by a slope of the characteristic 2400 obtained at that time. When the control voltage Vcntl is V2, the oscillation frequency fosc is f2 and a VCO gain 2402 is represented by a slope of the characteristic 2400 obtained at that time. The VCO gains 2401 and 2402 each are represented by the amount of fluctuation in oscillation frequency fosc relative to the control voltage Vcntl. The frequency f2 is lower than the frequency f1. The VCO gain 2402 at the low frequency f2 is lower than the VCO gain 2401 at the high frequency f1. As a result, as shown in FIG. 23, when the cutoff frequency is made constant in the high-band PLL circuit, jitter increases at low frequencies.
FIG. 25 is a diagram showing a control voltage Vcntl-amount of delay characteristic 2500 of the voltage-controlled delay device 121. The DLL circuit can lock in an amount-of-delay range TD in a tuning range RN. Vdd represents the power supply voltage and Vth represents the threshold voltage of transistors. When the control voltage Vcntl is V1, the amount of delay is T1 and a VCDL gain 2501 is represented by a slope of the characteristic 2500 obtained at that time. When the control voltage Vcntl is V2, the amount of delay is T2 and a VCDL gain 2502 is represented by a slope of the characteristic 2500 obtained at that time. The VCDL gains 2501 and 2502 each are represented by the amount of fluctuation in the amount of delay relative to the control voltage Vcntl. As such, when the cutoff frequency is made constant in the high-band DLL circuit, since the VCDL gain fluctuates according to the amount of delay, jitter increases with the amount of delay.
As shown in the following equation, parameters that determine a cutoff frequency BW are a charge pump current Icp, a resistance R of the low-pass filter 103, a VCO gain (or VCDL gain) K, and a frequency division number N (the case of the PLL circuit). Of them, since only the VCO gain (or VCDL gain) K does not have a fixed value, the cutoff frequency BW fluctuates.BW=Icp×R×K/(2×π×N)
Japanese Laid-Open Patent Publication No. 2005-236431 describes a frequency synthesizer in which a PLL loop includes an oscillator that generates a reference signal; a frequency/phase comparator that compares phases between the reference signal and a signal obtained by frequency-dividing an output signal and outputs a phase difference signal; a charge pump that generates a charge pump current according, to the phase difference signal; a low-pass filter that includes a fixed resistor and a fixed capacitor and that performs smoothing and voltage conversion on the charge pump current and outputs a control voltage signal; a voltage-controlled oscillator that generates the output signal having a frequency according to the control voltage signal; and a variable frequency divider that frequency-divides the output signal. The frequency synthesizer includes a variable resistor that is provided between an output terminal of the charge pump and one terminal of the fixed capacitor composing the low-pass filter and that variably sets a plurality of values according to a resistor control signal; and a variable resistor switching time control circuit that outputs the resistor control signal that controls the switching width and switching time of the variable resistor such that the loop gain increases when the frequency of the frequency synthesizer is switched and thereafter gradually decreases.
Japanese Laid-Open Patent Publication No. 2006-33197 discloses a PLL circuit including a phase comparator; a loop filter; a voltage-current conversion circuit that converts a control voltage output from the loop filter into a current; and a voltage-controlled oscillator having a current source appropriate for the output current output from the voltage-current conversion circuit, and having one or more ring-connected differential inverter circuits. The voltage-current conversion circuit has a variable resistor circuit that determines the output current, and reduces process variations.
Japanese Laid-Open Patent Publication No. 2006-222939 discloses a PLL circuit including a phase comparator that compares phase differences between an input signal and a frequency-divided signal and outputs a phase-advanced signal or a phase-delayed signal; a charge pump circuit that outputs a current signal according to the phase-advanced signal or phase-delayed signal output from the phase comparator; a low-pass filter that has a resistor and a capacitor and that smoothes the current signal output from the charge pump circuit and converts the smoothed current signal into a voltage signal; a voltage-controlled oscillation circuit that generates an oscillation signal with a frequency according to the voltage signal output from the low-pass filter; a frequency divider that frequency-divides, by a predetermined frequency division ratio, the oscillation signal output from the voltage-controlled oscillation circuit, to generate the frequency-divided signal; a frequency determination means of determining a change in the frequency of the input signal; and a switching means of switching, according to the determination made by the frequency determination means, at least two circuit constants among a current value of the current signal output from the charge pump circuit, a resistance value of the resistor, a capacitance value of the capacitor, and a frequency division ratio of the frequency divider. When the circuit constants are switched, the switching means simultaneously switches the circuit constants so as to change the band frequency of a PLL loop with the damping factor of the PLL loop being constant.